Modern electronic devices, and particularly, integrated circuits, are at risk of damage due to electrostatic discharge (ESD) events. During an ESD event, a voltage (or current) may be provided to one or more terminals of an electronic device that causes the voltage between those terminals (or other terminals of the electronic device) to exceed the designed maximum voltage of the device, which could impair subsequent operation of the device. For example, a voltage at a terminal of an electronic device during an ESD event may exceed the breakdown voltage of one or more components of the device, and thereby potentially damage those components. Accordingly, electronic devices include discharge protection circuitry that provides protection from excessive voltages and/or currents across electrical components during ESD events.
Modern electronic devices often include multiple different subsystems or subcircuits that are integrated into a single device to provide complex and/or broad ranges of functional capabilities, such as, for example, a system on a chip (SoC). In practice, different subcircuits may have different component sizes, performance requirements, and the like, and as such, may be designed for different voltage levels relative to other subcircuits of the device, resulting in different so-called “power domains” within a device. To achieve the desired functionality, circuitry from different power domains needs to be able to communicate signals to/from one power domain to another power domain. However, the interfaces between different power domains are susceptible to ESD voltages, which may propagate from one voltage (or power) domain, alternatively referred to as the transmitting or transmitter domain, to another voltage (or power) domain, alternatively referred to as the receiving or receiver domain, and thereby damage one or more components of the receiver domain.
One approach to protecting a cross-domain communications interface involves introducing a series resistance and clamping circuit that reduces ESD voltage at the receiver power domain and conducts discharge current away from the receiver power domain. However, the resistance and clamping circuitry create a filter that limits the bandwidth of the communications interface. Accordingly, other approaches attempt to provide other configurations of clamping circuits triggered by other available voltages to avoid interfering with normal operation of the communications interface. However, such approaches are often susceptible to noise and require undesirably-sized transistors to avoid ESD-related damage.
To avoid interfering with normal operation of the device being protected, the discharge protection circuitry is typically designed to turn on and conduct current when the applied voltage exceeds the operating voltage of the device but before the applied voltage exceeds the breakdown voltage of the device. However, there is often a period of time between when the applied voltage exceeds the operating voltage of the device and when the applied voltage reaches the transient triggering voltage that fully turns on the discharge protection circuitry. During this time, the components of the device may be exposed to a portion of the discharge current, which, in turn, could undesirably impact the functionality of the components in the future. Existing approaches often involve tuning the breakdown voltages of the discharge protection circuitry to achieve the desired ESD performance; however, this often incurs area penalties or otherwise increases costs associated with the discharge protection circuitry.